Operating Systems: Phase 1 & Phase 2
A C job-execution simulator progressing from instruction decoding to paging, interrupts and resource-limit handling.
2024
Four-character instructions, page-table translation and a central interrupt monitor.
A two-phase job execution simulator
The Operating Systems project implements a compact machine and monitor in C. Phase 1 establishes job loading and instruction execution over fixed memory. Phase 2 introduces paged address translation, frame allocation, a process control block and interrupt-driven job termination. The phases expose how a simple instruction moves through memory, register state and monitor services.
Phase comparison
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| Mechanism | Phase 1 | Phase 2 |
|---|---|---|
| Memory | 100 four-character words | 300 physical words and a 100-word virtual address space |
| Execution state | Instruction register, general register, counter and condition flag | Execution registers plus page-table register and process control block |
| Addressing | Direct memory access | Ten-word frames with virtual-page translation |
| Monitor | Read, write and halt services | Service, program and time interrupts with termination reasons |
Architecture and execution path
- The loader recognizes $AMJ, $DTA and $END control cards, separates program cards from input data and initializes the execution state for each job.
- Fetch/decode uses four-character instructions. GD and PD invoke data input/output; LR and SR move words through the general register; CR updates the condition flag; BT performs a conditional branch; H halts.
- Phase 2 maps a virtual address through its page-table entry. The real address is the frame number multiplied by ten plus the offset within the page.
- A valid GD/SR page fault allocates an unused frame and updates the page table. An invalid fault reaches the monitor's termination path instead of becoming an arbitrary memory access.
- The monitor combines service, program and time-interrupt state. The process control block holds job identity, time/line limits and counters used during execution.
Core mechanisms
- A frame-occupancy tracker prevents reusing an allocated frame during a job.
- Virtual addresses are checked against the 100-word address space before page-table translation.
- Opcode and operand errors produce program interrupts; data exhaustion and output-line limits have separate termination reasons.
- Instruction accounting updates the job time counter, with different costs for the defined instruction classes.
- The time/service interrupt combinations distinguish immediate termination, permitted final output and normal halt behavior.
Engineering decisions
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| Decision | Reason |
|---|---|
| Four-character words and a small instruction set | Make register changes and execution traces inspectable. |
| Paging added as a second phase | Separate the basic execution loop from virtual/physical address translation. |
| Central monitor for interrupts | Keep instruction decoding separate from service dispatch and termination policy. |
Implementation deliverables
OS_Phase1.c and OS_Phase2.c contain the loader, register state, instruction handlers and monitor. The second phase adds page allocation/translation and resource-limit handling. These source files provide a concrete progression from a directly addressed machine to a paged job-execution model.